mitsubishi digital assp ? M66006P/fp 12-bit i/o expander 1 mitsubishi digital assp ? M66006P/fp 12-bit i/o expander description the m66006 is a semiconductor integrated circuit which has 12-bit shift register function to execute serial-parallel conver- sion and parallel-serial conversion. because a serial-parallel shift register and a parallel-serial shift register are independently built in this ic, it is possible to read serial input data to a shift register while converting par- allel data into serial data. also, parallel data i/o pins can be set to input mode or output mode bit-by-bit. the m66006 can be widely used for i/o port expansion of mcu, serial bus system data communication, etc. features ? bi-directional serial data communication with mcu ? read of serial data during parallel-serial conversion. ? bit resolution of serial data i/o ? low power dissipation (50 m w/package max.) (v cc =5v, t a =25 c, in quiescing) ? schmitt input (di, clk, s, cs) ? open drain output (do, from d1 to d12) ? parallel data i/o (from d1 to d12) ? wide operating supply voltage range (v cc =2 to 6v) ? wide operating temperature range (t a =C20 to 75 c) application serial-parallel data conversion, parallel-serial data conver- sion, serial bus control by mcu. pin configuration (top view) block diagram clock input clk serial data output shift register ! parallel output latch shift register @ control circuit set input s chip select input serial data input do d1 do d1~ d12 d2 d3 d10 d11 d12 d 12 d 11 d 10 d 3 parallel data i/o d 2 d 1 d 1 do d 12 d 11 d 10 d 3 d 2 d 1 q 12 q 11 q 10 q 3 q 2 gnd gnd q 1 q 12 d 11 d 10 q 3 q 2 q 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? y ? ? ? ? ? ? ? ? ? ? ? ? ? ? t cs di clk s cs di v cc v cc v cc v cc input form output form 5 3 6 4 2 20 19 18 11 9 8 10 7 1 outline 20p4 20p2n-a do di d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 clk cs s d12 d11 do ? di ? clk ? cs ? v cc s ? gnd d12 ? d11 ? gnd ? d1 ? d2 ? d3 ? d4 ? d5 ? d6 ? d7 ? d8 ? d9 ? d10 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? y ? ? ? ? ? ? ? ? ? ? ? ? ? ? t serial data output 120 219 318 417 516 615 714 813 912 10 11 serial data input clock input chip select input set input parallel data i/o parallel data outputs
2 mitsubishi digital assp ? M66006P/fp 12-bit i/o expander function the m66006 realizes low power dissipation and high noise immunity by applying silicon cmos process. because a 12-bit serial-parallel shift register and a 12-bit par- allel-serial shift register are independently built in this ic, it is possible to read serial input data while converting parallel data into serial data. when cs changes from h to l, serial output of 12-bit par- allel data and read of serial data from the mcu start. that is, 12-bit parallel data is latched at the falling edge of cs, syn- chronized with the falling edge of shift clock, and then output to serial output pin do as serial data. at the same time, serial data from the mcu is read to the internal shift register at the rising edge of shift clock. the shift clock on and after 13th bit is neglected and pin do is put in the high impedance state when the reading operation is masked. when cs changes from l to h, 12-bit serial data read into pin di is output to parallel output pins from d1 to d12. because the output form of parallel output pins is n-channel open drain output, h must be written to the pin to set to in- put mode. description of operation (1) when power is supplied, pins do and from d1 to d12 are in undefined state. when s changes to l, those pins are in high impedance state. (2) at the falling edge of cs, the status of pins from d1 to d12 is loaded to shift register ! . (3) at the falling edge of clk, data which is loaded as above (2) is output to pin do as 12-bit serial data in order. (4) at the rising edge of clk, 12-bit serial data is written from di to shift register @ . (5) clk on and after the 13th bit is neglected and writing of serial data is not possible. also, do is put in the high im- pedance state. (6) at the rising edge of cs, the data which is written as men- tioned in (4) is output to pins from d1 to d12. (7) shift register ! loads the data applied externally and the and-tie data latched by the parallel output latch. (8) when cs rises before clk reaches the 12th bit, the paral- lel output latch latches the data which has been written to shift register @ and outputs it to pins from d1 to d12. in this case, shift registers ! and @ continues the shift op- eration and do outputs serial data until clk reaches the 12th bit. (9) switching of i/o mode of pins from d1 to d12 is controlled by the serial data which is input to pin di. pins to which h is written operates as input pins. operation timing diagram 1 clk cs s l h do1 do2 do3 do4 do5 do6 do7 do8 do9 do10 do11 do12 di1 di do di1 di2 di12 d1 d2 di2 do1 do2 do12 di2 di3 di4 di5 di6 di7 di8 di9 di10 di11 di12 2345678910111213 (2) (4) (6) (3) (5) (6) (1) high impedance 1 cycle
mitsubishi digital assp ? M66006P/fp 12-bit i/o expander 3 test conditions v o =0.1v, v cc C0.1v |i o |=20 m a v o =0.1v, v cc C0.1v |i o |=20 m a v o =0.1v, v cc C0.1v |i o |=20 m a v o =0.1v, v cc C0.1v |i o |=20 m a v i =v t+ , v tC v cc =4.5v v i =v t+ , v tC v cc =6v v i =v cc , gnd, v cc =6v conditions v i <0v v i >v cc v o <0v v o >v cc gnd ratings C0.5 ~ +7.0 C0.5 ~ v cc + 0.5 C0.5 ~ v cc + 0.5 C20 20 C20 20 C48 C60 ~ 150 symbol v cc v i v o i ik i ok i gnd t stg parameter supply voltage input voltage output voltage input protection diode current output parasitic diode current gnd current storage temperature unit v v v ma ma ma c absolute maximum ratings (t a = C20 ~ 75 c unless otherwise noted) recommended operational conditions symbol v cc v i v o t opr parameter supply voltage input voltage output voltage operating temperature limits min. 2 0 0 C20 typ. max. 6 v cc v cc 75 unit v v v c symbol v t+ v tC v ih v il v ol i o i cc parameter positive direction threshold voltage *1 negative direction threshold voltage *1 h input voltage *2 l input voltage *2 l output voltage maximum output leak current static power dissipation electrical characteristics (v cc = 2 ~ 6v unless otherwise noted) limits max. 0.8 v cc 0.65 v cc 0.25 v cc 0.5 10.0 C10.0 100.0 min. 0.35 v cc 0.2 v cc 0.75 v cc max. 0.8 v cc 0.65 v cc 0.25 v cc 0.4 1.0 C1.0 10.0 typ. unit v v v v v m a m a min. 0.35 v cc 0.2 v cc 0.75 v cc t a =25?c t a = C20~75?c i ol =3ma v o =v cc v o =gnd *1: di, clk, cs, s *2: d1~d12 symbol f max t plz t pzl t plz t pzl t plz parameter maximum repeat frequency output l-z, z-l propagation time clk-do output l-z, z-l propagation time cs-d1 to d12 output l-z propagation time s-do, d1 to d12 switching characteristics (v cc = 5v) unit mhz ns ns ns ns ns limits max. 400 400 400 400 400 min. 1.9 max. 300 300 300 300 300 typ. min. 2.5 c l =50pf r l =1k w (note 2) t a =25?c t a = C20~75?c test conditions
4 mitsubishi digital assp ? M66006P/fp 12-bit i/o expander timing conditions (v cc = 5v) limits note 2: test circuit symbol t w t su t h t rec parameter clk, cs, s pulse width setup time of di to clk setup time of cs to clk setup time of d1 to d12 to cs hold time of di to clk hold time of cs to clk hold time of d1 to d12 to cs recovery time of cs to s unit ns ns ns ns max. min. 260 130 130 130 130 130 130 130 max. typ. min. 200 100 100 100 100 100 100 100 test conditions t a =25?c t a = C20~75?c (1)characteristics of pulse generator (pg) (10% to 90%) t r =6ns, t f =6ns, z o =50 w (2)static capacitance cl includes floating capacitance of wiring and input capacitance of probe. tested device v cc output v cc input r l c l gnd pg 50 w
mitsubishi digital assp ? M66006P/fp 12-bit i/o expander 5 timing charts 50% clk 50% 50% gnd 50% 50% do s cs 10% t plz t pzl t rec t w t w 50% 50% 50% 50% 50% 50% cs 50% 50% 50% 50% v cc v ol ? v cc gnd v cc v ol ? v cc gnd v cc v ol ? v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc gnd v cc d1 ~ d12 di clk s do d1 ~ d12 10% 10% t plz t plz t pzl t w t w t w t su t h 50% 50% 50% d1 ~ d12 cs t su t h 50% 50% 50% 50% cs clk t su t h
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